DRAM (dynamic random access memory) is a memory, which transmits or receives a digital signal through a bus according to the requirement of a central processing unit (CPU) in a system. Under the standpoint of signal (bit) transmission, the DRAM is focused on the optimization of electric signal transmission such as a data width or driving force of a data output buffer. Namely, there is a demand for speedy and precise with regard to signal-to-noise ration (S/N ratio), signal transmission according to the requirement of the CPU. However, as the DRAM has been applied to a network system, speedy and precise “information” transmission becomes more important than speedy and precise “signal” transmission. Under the standpoint of information transmission, there is a demand for smooth data transmission between the DRAM and transmission objects. Accordingly, many efforts have been made for enhancing transmission efficiency without idle time on a bus.
A conventional DDR (double data rate) DRAM is now described below with reference to FIG. 1.
Referring to FIG. 1, a DDR DRAM 100 transmits address signals ADD to a bank selecting unit 120, a row buffer 130, and a column buffer 140 in response to a clock signal CLK inputted from an address register 110. An output of the bank selecting unit 120 and an output of the row buffer 130 are decoded by a row decoder 150, and an output of a column buffer is decoded by a column decoder 160. In a memory block 170 having a plurality of banks, memory cells corresponding to a wordline activated by the row decoder 150 and a bitline activated by the column decoder 160 are selected. In a write operation, data DQi inputted to a data input register 230 is written to selected memory cells. In a read operation, data of the selected memory cells are outputted to the data input/output signal DQi through a sense amplifier (S/A) 180 and an output buffer 220. The outputted data input/output signal DQi may be variously embodied with latency information and burst length information 210. The latency information and the burst length information are stored in a programming register 200 according to the inputted clock signal CLK and a plurality of control signals CKE, /CS, /RAS, /CAS, and /WE, through the timing register 190.
The operation of the DDR DRAM 100 is now described with reference to FIG. 2. For the convenience, the DDR DRAM 100 is described under the example that a row clock cycle (tRC) is set to 10 clock cycles (10*tCK), an /RAS to /CAS delay time (tRCD) is set to 3 clock cycles (3*tCK), and a CAS latency (CL) is set to 3.
Referring to FIG. 2, a first active row command A0 is inputted at a clock 0. After tRCD time elapses from the clock 0, a read command R0 relative to a first active low state is inputted at a clock 3. After a clock cycle corresponding to “CL=3”, first data Q0 is outputted to a data input/output signal DQi at a clock 6. A second active row command A1 is inputted at a clock 10 which is reached from the clock 0 after tRC time elapses. A read command R1 relative to a second active low state is inputted to a clock 13 which is reached from the clock 0 after tRCD time elapses. After the clock cycle corresponding to “CL=3”, second data Q1 is outputted at a clock 16.
If a network system is realized by applying such a DDR DRAM with trend toward the high speed of a communication apparatus, data access time is shortened to shorten data transmission time. Thus, a high-speed operation can be achieved. Under the standpoint of the network system, it is expected that data transmitted through bus lines in the system will be transmitted without suspension or idle time, i.e., a high bus efficiency will be achieved.
In view of the foregoing operation timing of the DDR DRAM (100 of FIG. 1), bus efficiency between first data Q0 and second Q1 loaded on the data input/output signal DQ1 is merely 20% (i.e., the first data Q0 is loaded only on two clocks out of ten clocks). Since only one access is possible for one tRC time, the amount of data transmitted per unit time is reduced. Therefore, the DDR DRAM is not suitable for the network system.